Monday, February 11, 2013

Frequency counter using Avnet S3A EVK

My love affair with digital electronics continues. I found Mike Field's wiki entry for a frequency counter using an FPGA. I was struck by how inexpensive the DealExtreme 8-digit display Mike used was. $7 including shipping! So of course I had to order one.

Well it arrived last week. Took me a day to find out the connector cable they included was faulty. The first project I tried simply followed Ricardo Batista's Arduino code for the TM1638 chip on the dxdisplay. I used a Freetronics LeoStick I purchased from Jaycar a year ago. Turns out the dxdisplay uses a lot of current, more than my MacBook Air can supply from its USB ports. Luckily I had also purchased Freetronics' PRV28 power regulator at the same time and it was able to supply enough current.

Then I remembered I had an old Avnet Spartan3A Eval Kit I had purchased in 2008 for $39. At the time I had no idea what to do with it so it languished in the junk pile. I fished it out and I was amazed! The components on the board are still (almost) state of the art. FPGA, switching regulators, SPI and BPI flash, capacitive touch buttons etc. etc. Five years later and it's still very modern. Only problem is Avnet and Xilinx have pretty well given up on Spartan 3A so a lot of the support material on their sites was hard to find. And to complicate matters the Cypress PSoC used to program the FPGA was loaded with outdated firmware no longer compatible with more recent software. So the first task was to update the firmware. That took days of Googling and experimentation. Then I was able to use a more recent version of Avnet's AvProg loader software. The exercise of getting Xilinx's ISE Design Suite installed on my laptop was Herculean but now it runs nicely on Parallels Desktop+Win 7.

So it occurred to me that connecting a $39 FPGA kit to a $7 8-digit display to make a 0-99MHz frequency counter might be an interesting exercise. As usual there has been a lot of yak shaving. First of all the clock on the EVK was only 16MHz whereas Mike's code expected 32MHz. He then used a standard DCM clocking module from Xilinx to synthesise a 244MHz clock frequency. Luckily the DCM multiplies upto 16 times so I was able to select 14 to get the same frequency (although I suspect jitter probably invalidates the clock accuracy). Mike also intends his code to use an external GPS module to supply a 1 pulse per second signal used to restart each count. But he pointed out that for less accuracy, simply connecting an internally generated 1pps signal to the 1pps input can suffice for a while.

Code available here.

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